1. Field of the Invention
The present invention relates to computer hardware design, and in particular to a printed circuit board connector circuit for arrangement between two printed circuit boards, said connector circuit comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes.
2. Description and Disadvantages of Prior Art
A prior art connective device between two printed circuit boards is depicted schematically and in a simplified way in FIG. 1. Details follow later below.
Such printed circuit boards are also referred to herein as “cards”. The present invention will be defined from prior art by referencing a card connector between a mother card and a daughter card as this relates to common practice.
In complex computer systems there is the need to supply a card with more than two voltage levels as represented by the nominal supply voltage and ground, but instead very often, a third voltage level V3 or even more voltage levels are needed to be implemented at the card. Signal wiring and voltage supply are often arranged in separate planes, and a card has a sandwich-like plane structure, wherein vias connect between different planes. Further, those voltages represent a voltage reference in relation to signal wiring, so the voltage planes are referred to herein also as reference planes.
Those reference planes are metallization planes which implement often one ground and two different voltage levels, often denoted as GROUND, Vdd and V3, thus e.g. GND=0 Volt, Vdd=1.8 Volt, and for example an intermediate voltage level V3 as e.g., V3=1.5 Volt.
With reference to the very focus of the present invention it is useful to make a distinction between different packaging levels, like Chip level, Multi Chip Modules (MCM), MCM connectors, card levels, card connectors, back plane boards, where different electrical situations prevail, but which must be electrically connected to each other for operation.
Further packaging levels are for instance (in a bottom up view): The chip as a zero packaging level, chip-module as a first packaging level, cards (so called printed wiring boards) carrying different multiple chip-modules as a second packaging level, or so called mother boards carrying different card connectors with daughter cards as a third level package.
When connecting two cards, i.e., two printed circuit boards of complex computer systems, a lot of performance critical high-frequency signals thus do not stay within one and the same packaging level.
More particularly, and with reference to FIG. 1 a first card 110 is shown connected to a second card 118 by aid of a connector device 111. A signal line 115 is depicted to cross from the first card 110 via the connector 111 to the second card 118. The same is true for a ground line 116 and a supply voltage line 117 and a further voltage line 119, having the voltage level denoted as V3.
Signals like that one depicted as signal 115 often pass the above-mentioned different packaging levels and components. In each of the packaging levels and components the signal is referenced to voltage and ground layers, pins or plated through-holes, abbreviated as PTH, adjacent to them. This is depicted in FIG. 1 symbolically with signal 115 and adjacent ground pin 116 and voltage pin 119.
In different cards and connectors the voltage level acting as a signal reference can vary, due to the need to distribute different voltage levels inside the cards and system, i.e., within the sandwich layer structure of the cards.
Cost-driven card and system designs often need special design solutions in order to find a trade-off between cost and the optimum electrical design. Therefore, so-called connector shields in the signal area are not only used as a signal high-frequency return current reference, but also as a current distribution for different voltage levels. Thus, signals 115 may have different references in mother card 110 and daughter card 118 as well as in the connector 111. Due to these discontinuities signal coupling, i.e. the so-called crosstalk, will disadvantageously increase dramatically.
With further reference to a publication in IBM Journal of Research and Development, Vol. 48, No. 3/4, published May, July 2004 and FIGS. 2, 3, 4 and 5 (table representation) three exemplary cases of a card-to-card connections are given having different electrical properties in terms of the before-mentioned high-frequency crosstalk problems. In the above publication the technological background for this problem is discussed.
In order to demonstrate the effects of non ideal high frequency signal return path measurements are disclosed performed on a special card test vehicle consisting of two cards connected with a card connector.
FIG. 2 (case 1) is a partly cross sectional view including a multi layer structure illustrating a signal wiring 35 from a more top layer to a more bottom layer, crossing the intermediate layers by a via (depicted as vertical line), illustrating the schematics of the electro-magnetic field around the signal wiring and the associated high frequency signal return path in the layers adjacent to the signal wire, in an ideal case, wherein the signal wiring 35 is embedded always between two power planes; these could also be two ground planes. Here the return path is basically closed all over the signal 35 travel from card 1, over the via of the connector until reaching card 2, as the signal is embedded always by the same voltage reference (either Ground, or Power).
FIG. 3 (case 2) is a depiction according to FIG. 2 including a voltage plane 32 separating signal line 35 and an additional signal wiring 36 in the card 2 portion. In the top portion of card 1 the same good closing of the return path is achieved.
In the bottom portion of card 2 however, the signal 36 is embedded between a ground plane 20 and a voltage plane 30. This implies a return path for signal 35 which is slightly worse than in FIG. 2.
FIG. 4 is a depiction according to FIG. 3 but including a floating pin 40 and illustrating a “worst” case high frequency signal return path for signal 35. Floating can be assumed to occur due to the fact that pin 40 is connected to a reference voltage or to Ground in a quite long distance only. From this floating state a high noise coupling results from signal line 35 to signal line 36 within a discontinuity region within a circle 42 depicted by a broken line. The exact results are given in the table of FIG. 5. Near end is understood to be within card 1, and far end is within card 2.
Measurements performed for the case 2 prove that the high frequency return is nearly as good as for the ideal case 1.
In contrast to that, measurements performed for the case 3 show a significant increase of coupled noise.
In case 3 the floating pin 40 is not connected to any reference plane in card 1 or 2. Therefore the high frequency return current in all other adjacent pins will be increased and thus signal coupling will be increased, if the next neighbouring pins are signal pins. In table 1 the near and far end coupling is depicted for all three cases. In comparison, while the differences in coupling in cases 1 and 2 are negligible, the coupling increases significantly in case 3 by a factor of 4 (near end) and 10 . . . 11 for the far end. Usually, a floating pin 40 is not used in the system design. From a high frequency return path of view, however, a connector pin connected to a voltage or ground plane far away from the internal signal wire connected to the signal pin behaves like a floating pin. This means with increasing distance of the pin (carrying the high frequency return signal) to the power/ground connection, the signal coupling will also increase.
A further printed circuit board structure is disclosed by incorporation in a product sold by IBM, available under IBM eServer zSeries z990 discloses the technical context illustrated in FIGS. 6 and 7. In this publication so-called soft switches are mentioned which are used to drive down the card voltage, when the card has to be replaced in a running system or to prevent cards from being damaged or from malfunctions caused by “over-current”. The soft switch separates the card 1 internal voltage 2, FIG. 6, from the source voltage 1 in card 2. The high frequency return path of the signal path—when passing from card 1 to card 2—is said to be broken, which would result in an increased signal coupling. In order to limit the signal coupling it is disclosed to add a second voltage plane as shown in prior art FIG. 7. Thus, a complete plane pair exists having a level of voltage 1 an voltage 2, respectively, which is said to limit the impedance mismatch and the signal-to-signal coupling at the card discontinuity and to provide a good high frequency signal return path due to an efficient internal plane capacitance. This solution is, however, not applicable for cost-driven card designs as the additional plane increases the costs.
It is thus desired to close the high frequency signal return path around a signal path 115 from card to card including the connector, in order to limit the signal coupling while concurrently keeping the card design as simple as possible.